The Human Body Model ESD test is popularly known as HBM. Several widely available test specifications are available for the performance of HBM testing. The most widely used test method is the EIA/JEDEC JESD-A114 test. Other methods include the ANSI/ESDA STM5.1, MIL-STD-883 and AEC-Q100-002. These specifications are regularly updated by industry standards organizations, so revisions may change periodically. Semiconductor companies perform ESD testing of sample devices for each new product as part of a standard production release process, as required by their customers. Required Human Body Model immunity levels typically range from 1000V to as high as 8000V, depending upon the end customer applications.
In today’s high volume production assembly and test environments, semiconductor products rarely come into contact with human beings. However, ESD protection requirements for HBM are still required for two main reasons: (1) the ESD protection designs that protect with respect to HBM also come into play for Charged Device Model, or CDM, issues which are one of the major causes of semiconductor yield loss in back-end manufacturing, and (2) it is still necessary in many cases to handle semiconductor products in the development and evaluation laboratories during new product development and customer product sampling.
The failure modes for HBM typically consist of junction failures within the semiconductor devices and visible thermal damage that has occurred during the ESD event. For example, a 2,000 V pulse into a short can result in currents above 1.4 A, which discharges a large amount of current into the IC in a short time period of several hundred ns (although still a relatively slow discharge).
Human Body Model testing requires that each pin on the IC is tested in a very specific manner. The IC is installed on a specially designed load board, which interfaces with an automated high-pin-count ESD tester. Each pin is tested with high voltage and high current ESD shocks, while other pins on the board are held to ground. Essentially, each pin is zapped with respect to groups of independent power and ground supplies, as well as each pin being zapped while all of the other I/O pins are grounded. For example, an IC with 2,000 pins may have 30-50 independent power/ground groups that are designed to run independently of each other. This results in a large matrix of testing combinations, and equates to a very lengthy and involved ESD testing. Therefore, each pin on an IC may be zapped thousands of times during HBM testing. Also keep in mind that ESD testing is ultimately a destructive test, so testing requires multiple units to be tested.
There are two main purposes for Human Body Model ESD testing of an IC. The first is to determine ESD immunity of the IC, which ensures that the product is manufacturable and can be confidently brought to market. The second purpose is to identify what the failure mechanisms are on the Device Under Test, or DUT. The data that is collected from this testing generally consists of leakage measurements and strategic curve trace sweeps, performed before and after testing, to help identify the particular combinations of ESD pulses that result in damage to the IC. This data can then be reported back to the ESD protection designers so they can improve their strategy for the protection design of the unit.
Additional Overviews:
- ESD Testing
- Human Body Model
- Charged Device Model
- Machine Model
- Latch up
- Transmission Line Pulse