Machine Model was developed in the 1990s as a way of modeling what happens in auto manufacturing facilities when a machine becomes electrostatically charged, and discharges into an IC when it comes in contact with it. This model is used less today, but is still relevant to the overall ESD testing landscape. This is essentially modeled by a charged capacitor and an inductive discharge, which is more indicative of the characteristics of a machine than a human.
The Machine Model ESD test is popularly known as MM. Several widely available test specifications are available for the performance of MM testing. The most widely used test method is the EIA/JEDEC JESD-A115 test. Other methods include the ANSI/ESDA STM5.2, and AEC-Q100-003. These specifications are regularly updated by industry standards organizations, so revisions may change periodically. Semiconductor companies perform ESD testing of sample devices for each new product as part of a standard production release process, as required by their customers. Required MM immunity levels typically range from 50V to as high as 400V, depending upon the end customer applications.
The failure modes for MM typically consist of junction failures within the semiconductor devices and visible thermal damage that has occurred during the ESD event.
Machine Model testing requires that each pin on the IC is tested in a very specific manner. The IC is installed on a specially designed load board, which interfaces with an automated high-pin-count ESD tester. Each pin is tested with high voltage and high current ESD shocks, while other pins on the board are held to ground. Essentially, each pin is zapped with respect to groups of independent power and ground supplies, as well as each pin being zapped while all of the other I/O pins are grounded. For example, an IC with 2,000 pins may have 30-50 independent power/ground groups that are designed to run independently of each other. This results in a large matrix of testing combinations, and equates to a very lengthy and involved ESD testing. Therefore, each pin on an IC may be zapped thousands of times during MM testing. Also keep in mind that ESD testing is ultimately a destructive test, so testing requires multiple units to be tested.
There are two main purposes for Machine Model ESD testing of an IC. The first is to determine ESD immunity of the IC, which ensures that the product is manufacturable and can be confidently brought to market. The second purpose is to identify what the failure mechanisms are on the Device Under Test, or DUT. The data that is collected from this testing generally consists of leakage measurements and strategic curve trace sweeps, performed before and after testing, to help identify the particular combinations of ESD pulses that result in damage to the IC. This data can then be reported back to the ESD protection designers so they can improve their strategy for the protection design of the unit.
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