Today’s semiconductor products are become increasingly complex, with more functions being integrated into each component. Integrated Circuits, referred to as Systems on Chip (SoC) or systems in package (SiP), are reaching new levels of integration, where various types of circuit blocks are combined inside a single package on a single die or combinations of multiple dice. These include RF, analog, digital, optoelectronic, and microelectronic devices. Also, the process technologies are scaling according to Moore’s Law, with devices operating in very low voltage regions of 1 V and below. This advancing level of circuit complexity is pushing technology to a new echelon, which affects the Electrostatic Discharge (ESD) immunity of semiconductor ICs, and the ESD testing service solutions White Mountain Labs offers the semiconductor industry.
Take for example, a scenario where you walk across a carpet and touch a light switch. It is likely that you will experience a slight zap, which is the ESD from your body into the switch. That seemingly small zap is more than sufficient to destroy todays ICs if they are handled inappropriately. So how does this ultimately affect the semiconductor industry? Research shows that up to 25 percent of field returns are due to ESD damage, which results in huge costs to semiconductor manufacturers in terms of materials, recycling, and protecting against ESD in manufacturing areas. Not to mention the adverse effects it can have on a vendor’s reputation and repeat sales to end users. In turn, ESD protection can cost manufacturers up to 10 percent of their annual revenue in terms of protection, designing prevention methods, and processing field failures.
ESD testing standards include models that have been developed for Human Body Model (HBM), Machine Model (MM), and Charge Device Model (CDM). The elements that define these tests include a real-world example of a charged capacitance and a discharge path that occurs.
Standards and Practices
There is a set of standards in place that defines how ESD tests should be conducted for qualification testing. These standards, set forth by JEDEC and the ESD Association, form the basis of the ESD testing sequences performed. Typically, testing for HBM and CDM are both required for certification of a new IC.
For example, a vendor will submit several fully functional ICs to an ESD testing service such as White Mountain Labs. The tester will be calibrated and verified using an oscilloscope, and the high voltage discharge waveforms will be verified before testing begins. The ICs are then installed, and ESD testing commences. The first sequence will be to sweep current and measure voltage, to develop a series of curve traces for each of the pins on the IC. When the voltage application sequencing beings, various curve traces are taken throughout the process in order to identify worst-case failing conditions. If the curve-trace shifts after the ESD pulse is applied, it is assumed that a failure has occurred. Comparisons can be made throughout the testing process to identify shifts or shorts that may have developed as a result of the ESD pulses. After testing is complete, the ICs are sent to the automated test floor to have final parametric and functional testing performed (ATE testing), which is the final verification of a passing or failing test for the IC.
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