Although latch-up testing is performed on the same automated testers as ESD testing, the tests are dramatically different. ESD testing is an un-powered test, whereby pins receive voltage pulses with complex combinations of grounded pins on the device under test (DUT). Latch-up testing is performed with the DUT powered, and signals applied to the part to place it in a stable, low current configuration. Specialized automated testers, such as the Thermo Scientific Mk2 or Mk4, are used for ESD and Latch-up testing because each tester channel has the unique ability to be programmed as a power supply, signal pin, or stress pulse generator.
The goal in latch-up testing is to trigger and monitor a latch-up event, where the stress pulse activates a parasitic “Silicon Controlled Rectifier” (SCR) structure within a CMOS or Bi-CMOS process technology. Latch-up testing is fundamentally about the chip physical layout, how circuit blocks are situated relative to one another, and how unanticipated charge is removed from physical elements in the semiconductor material.
The fundamental issue in performing a latch-up test is to render the DUT insensitive to the latch-up pulse as a valid signal. What does this mean? The DUT must be placed in a stable, low current condition so that the latch-up trigger pulse does not cause the DUT to change circuit operating conditions. If the latch-up trigger pulse is perceived by the DUT to be a valid signal, then the operation of the DUT may change, causing a change in the power supply currents. Any significant change in the power supply current may be flagged as a latch-up failure. So, if the DUT changes operating modes due to the latch-up pulse, a false latch-up failure may be reported. If the DUT is sufficiently stabilized, due to the application of appropriate control signals or vectors, then the latch-up trigger pulse will not affect the power supply current – unless a latch-up event due to parasitic physical structures is initiated.
The primary electronics industry standard for latch-up testing is the EIA/JEDEC JESD78 (please refer to the most current revision when searching on the JEDEC web site: http://www.jedec.org).
For qualifying a latch-up test service, it is important to review the technical competency and latch-up test experience of the engineering staff, since the latch-up test requires a unique combination of abilities in device physics, circuit design, and latch-up test methods.
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